The SCBench benchmark includes a comprehensive suite of SystemC and TLM designs for SystemC verification and validation. These designs are selected from a wide variety of application domains and cover as many SystemC core features as possible. Key features of SCBench are described as follows.
- SCBench consists of 38 well-written representive SystemC and TLM designs from various application domains, such as CPU architecutre, security, DSP, image processing, network, and artificial intelligence.
- The designs range from small single process designs to large multi-process designs. All designs are selected carefully to cover as many SystemC features as possible.
- Each design has been provided a set of stimuli and a testbench including stimuli applications and output monitors.
- SCBench is freely available online to all researchers.
List of Benchmark Designs
The SCBench benchmark suite includes the following 38 SystemC and TLM designs. The detailed descriptions and characteristics of each design can be found in our paper.
|RISC CPU||A CPU architecure that fetches instructions, decodes and executes them, then writes the results back to registers or memory||SEQ|
|RISC_CPU_control||The RISC CPU instruction decode unit||SEQ|
|RISC_CPU_mmxu||The RISC CPU MMX-like execution unit||SEQ|
|RISC_CPU_exec||The RISC CPU integer execution unit||SEQ|
|RISC_CPU_floating||The RISC CPU floating point execution unit||SEQ|
|IA-32||An instruction length decoder for Interl's IA-32 architecture||SEQ|
|MIPS||A simplified MIPS processor||SCBench|
|Y86||A simple CISC CPU implementing a subset of the insructions of the IA-32 architecture||SEQ|
|AES||An encryption algorithm implementing the advanced encryption statndard||Scoot|
|DES||A symmetric key encryption algorithm||Scoot|
|RSA||The RSA public key cipher||SystemC library|
|KASUMI||A block cipher algorithm||S2CBench|
|SNOW3G||A stream cipher||S2CBench|
|MD5C||The message digest algorithm that generates hash values||S2CBench|
|IDCT||Inverse discrete consine transform||S2CBench|
|Interpolation||An algorithm used to construct new data points within the range of a discrete set of known data points||S2CBench|
|ADPCM||Adaptive differential pulse-code modulation||S2CBench|
|FFT||Fast Fourier transform algorithm||S2CBench|
|ASR/ABS||An anti-slip regulation and anti-block braking system||STATE|
|UsbTxArbiter||An data processing algorithm used in a USB core||SEQ|
|UART||Universal asynchronous receiver/transmitter||S2CBench|
|Qsort||The quich sort algorithm sorting data in ascending order||S2CBench|
|Disparity||An algorithm computing the disparity in a 3D-image||S2CBench|
|Sobel||An edge detection algorithm||S2CBench|
|VGA||A VGA controller and image generator||S2CBench|
|NoC||A network on chip simulator||opencores.org|
|Master/Slave Bus||A generic bus structure||SystemC library|
|Pkt_switch||A 4 by 4 multicast helix packet switch||SystemC library|
|ANN||Artificial neural network||S2CBench|
|Crossroad||A four-way intersection scenario||Aegis|
|Philosophers||Dining philosophers problem||Aegis|
|Producer/Consumer||The classical producer/consumer scenario||Aegis|
|SimpleRing||A simple ring network||Aegis|
|TLM_b_transport||A loosely-timed model with the blocking transport interface||doulos.com|
|TLM_DMI_DBG||A TLM model exploring the response status of the generic payload, as well as the direct memory and the debug transport interfaces||doulos.com|
|TLM_nb_transport||An approximately-timed model with the non-blocking transport interface||doulos.com|
|AMBA_AHB||The advanced high performance bus of the advanced microcontroller bus architecture||STATE|
- A tarball with all designs: SCBench v1.0
- To download the most up-to-date version, please check here.
Please cite the following paper when you publish a paper where SCBench is used.
- Bin Lin, and Fei Xie. "SCBench: A Benchmark Design Suite for SystemC Verification and Validation". In Proceedings of the 23rd Asia and South Pacific Design Automation Conference (ASP-DAC'18), Jeju Island, Korea, January 2018.
If you have any questions or comments regarding to SCBench, please contact us (svl<AT>cs.pdx.edu).
- SEQ. http://www.cprover.org/hardware/sequential-equivalence.
- N. Blanc, D. Kroening, and N. Sharygina. Scoot: A Tool for the Analysis of SystemC Models. In Proceedings of International Conference on Tools and Algorithms for the Construction and Analysis of System, 2008.
- B. Schafer and A. Mahapatra. S2CBench: Synthesizable SystemC Benchmark Suite for High-Level Synthesis. IEEE Embedded Systems Letters, 2014.
- P. Herber, J. Fellmuth, and S. Glesner. Model Checking SystemC Designs Using Timed Automata. In Proceedings of the 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2008.
- Aegis test benchmark. https://github.com/mglukhikh/aegis-systemc-benchmark.