A Benchmark Design Suite for SystemC Verification and Validation


The SCBench benchmark suite has been developed for SystemC verification and validation. The designs included in the suite are selected from a wide variety of applications domains. Key features of SCBench are described as follows.

List of Benchmark Designs

The SCBench benchmark suite includes the following 38 SystemC designs. The detailed descriptions and characteristics of each design can be found in our paper.

Design Briefly Descriptions Sources
RISC CPU A CPU architecure that fetches instructions, decodes and executes them, then writes the results back to registers or memory SEQ[1]
RISC_CPU_control The RISC CPU instruction decode unit SEQ
RISC_CPU_mmxu The RISC CPU MMX-like execution unit SEQ
RISC_CPU_exec The RISC CPU integer execution unit SEQ
RISC_CPU_floating The RISC CPU floating point execution unit SEQ
IA-32 An instruction length decoder for Interl's IA-32 architecture SEQ
MIPS A simplified MIPS processor SCBench
Y86 A simple CISC CPU implementing a subset of the insructions of the IA-32 architecture SEQ
AES An encryption algorithm implementing the advanced encryption statndard Scoot[2]
DES A symmetric key encryption algorithm Scoot
RSA The RSA public key cipher SystemC library[3]
KASUMI A block cipher algorithm S2CBench[4]
SNOW3G A stream cipher S2CBench
FIR Finite impulse response filter S2CBench
IDCT Inverse discrete consine transform S2CBench
Interpolation An algorithm used to construct new data points within the range of a discrete set of known data points S2CBench
ASR/ABS An anti-slip regulation and anti-block braking system STATE[5]
UsbTxArbiter An data processing algorithm used in a USB core SEQ
UART Universal asynchronous receiver/transmitter S2CBench
Qsort The quich sort algorithm sorting data in ascending order S2CBench
Disparity An algorithm computing the disparity in a 3D-image S2CBench
Sobel An edge detection algorithm S2CBench
VGA A VGA controller and image generator S2CBench
NoC A network on chip simulator[6]
Master/Slave Bus A generic bus structure SystemC library
Pkt_switch A 4 by 4 multicast helix packet switch SystemC library
ADPCM Adaptive differential pulse-code modulation S2CBench
FFT Fast Fourier transform algorithm S2CBench
ANN Artificial neural network S2CBench
Crossroad A four-way intersection scenario Aegis[7]
Philosophers Dining philosophers problem Aegis
Producer/Consumer The classical producer/consumer scenario Aegis
SimpleRing A simple ring network Aegis
TLM_b_transport A loosely-timed model with the blocking transport interface[8]
TLM_DMI_DBG A TLM model exploring the response status of the generic payload, as well as the direct memory and the debug transport interfaces
TLM_routing Interconnect component
TLM_nb_transport An approximately-timed model with the non-blocking transport interface
AMBA_AHB The advanced high performance bus of the advanced microcontroller bus architecture STATE



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  1. SEQ.
  2. N. Blanc, D. Kroening, and N. Sharygina. Scoot: A Tool for the Analysis of SystemC Models. In TACAS, 2008.
  4. B. Schafer and A. Mahapatra. S2CBench: Synthesizable SystemC Benchmark Suite for High-Level Synthesis. IEEE Embedded Systems Letters, 2014.
  5. P. Herber, J. Fellmuth, and S. Glesner. Model Checking SystemC Designs Using Timed Automata. In HW/SW Codesign and System Synthesis, 2008.
  7. Aegis test benchmark.